1. Field of the Invention
The present invention relates to a Dynamic Random Access Memory (DRAM) as a semiconductor memory device and, particularly, to a DRAM for realizing data writing at a high speed.
2. Description of the Related Art
A DRAM is a semiconductor memory device for storing data in accordance with stored charges of capacity elements, and a memory cell normally comprises one capacitor and one transistor. In each memory cell, a control terminal (gate) of the transistor is connected to a word line and a memory cell is selected by an activation voltage applied to the word line.
FIG. 5 is a circuit diagram of a partial configuration of a normal DRAM. As shown in FIG. 5, the DRAM comprises a memory cell array 100a, a bit line equalizer 102, a sense amplifier 150a and a column selector 160a. 
Note that, in FIG. 5, a row decoder for selecting a word line and a column decoder for outputting a column selection signal YSEL for selecting a column are omitted.
The memory cell array 100a comprises a plurality of memory cells arranged in a matrix. Note that only two memory cells MC1 and MC2 are illustrated in FIG. 5 as an example.
As shown in FIG. 5, the memory cell MC1 comprises a transistor, for example, a nMOS transistor Tr1 and a capacitor Cs1 for holding charges. A gate of the transistor Tr1 is connected to a word line WLn, one electrode is connected to a bit line BL, and the other electrode is connected to the capacitor Cs1. One electrode of the capacitor Cs1 is connected to the transistor Tr1, and the other electrode is connected to a plate line. The plate line is kept, for example, at a voltage Vp.
The memory cell MC2 has approximately the same configuration as that of the memory cell MC1 as shown in FIG. 5, and comprises a transistor Tr2 and a capacitor Cs2. A gate of the transistor Tr2 is connected to a word line WLn+1 and one electrode is connected to a bit line BLB. Note that the capacitors Cs1 and Cs2 share a via and are connected to the plate line.
The word lines WLn and WLn+1 are selected by a not shown row decoder. An activation voltage is applied to a selected word line in accordance with a row address. Here, for example, the activation voltage is set at a voltage which is higher than a power source voltage VDD by an amount of a threshold voltage Vthn of the nMOS transistor composing the memory cells MC1 and MC2.
The bit lines BL and BLB form a bit line pair. The bit lines BL and BLB are equalized to be at a voltage Vb by the bit line equalizer 102. When reading, a voltage difference that has arisen between the bit lines BL and BLB is amplified by the sense amplifier 150a in accordance with stored data of a selected memory cell.
Between the bit line BL and a data line LIO is connected a transistor Q4 constituting the column selector 160a, and between the bit line BLB and a data line LIOB is connected a transistor Q5 constituting the column selector 160a. 
The equalizer 102 comprises transistors Q1, Q2 and Q3, as shown in FIG. 5. Gates of these transistors are connected to a signal line applied with a bit line equalization signal BLEQ. Since the bit line equalization signal BLEQ is in an activated state, that is, held at a high level before reading, the transistors Q1, Q2 and Q3 become conductive and the bit lines BL and BLB are held at an equalization voltage Vb. After starting to read, the bit line equalization signal is switched to be at a low level, the transistors Q1, Q2 and Q3 are cut off, and the bit lines BL and BLB become a floating state.
The sense amplifier 150a comprises pMOS transistors PT1 and PT2 and nMOS transistors NT1 and NT2, as shown in FIG. 5. These MOS transistors constitute a latch circuit comprising two inverters wherein input/output terminals are connected to each other. The bit lines BL and BLB are respectively connected to both terminals of the latch circuit. A drive voltage SDP is supplied to the pMOS transistors PT1 and PT2 side, and a drive voltage SDN is supplied to the nMOS transistors NT1 and NT2 side. Note that when operating the sense amplifier, for example, the drive voltage SDP is held at a power source voltage VDD and the drive voltage SDN is held at a ground voltage. On the other hand, when the sense amplifier is on standby, the drive voltages SDP and SDN are held, for example, at an intermediate voltage of the power source voltage VDD and the ground voltage.
When reading, the sense amplifier 150a is supplied with the drive voltages SDP and SDN and activated in accordance therewith. At this time, the sense amplifier amplifies a potential difference of the bit lines BL and BLB, so that stored data of a selected memory cell are read out to be output to the outside.
In the column selector 160a, the transistors Q4 and Q5 are controlled by a column selection signal YSEL. The column selection signal YSEL is supplied by a not shown column decoder. When reading and writing, a column selection signal YSEL corresponding to a selected column is activated, that is, held at a high level. In response to this, the transistors Q4 and Q5 become conductive, and when reading, voltages of the bit lines BL and BLB amplified by the sense amplifier 150a are respectively output to the data lines LIO and LIOB, while when writing, signal voltages of the data lines LIO and LIOB are respectively output to the bit lines BL and BLB.
FIGS. 6A to 6F are timing charts of a writing operation of the DRAM shown in FIG. 5. Note that an explanation will be made by taking as an example a writing operation by random accessing in the DRAM here.
Below, with reference to FIG. 5 and FIG. 6, a writing operation of the DRAM in random accessing will be explained.
Writing to the DRAM includes a reading operation. This is for refreshing stored data in memory cells connected to a selected word line but not intended to be written and ensuring credibility of data. Namely, when writing, reading is performed on all memory cells connected to the selected word line. After that, write data input from the outside are written in a selected memory cell, and read data are written in other memory cells.
As shown in FIG. 6, a bit line equalization signal BLEQ is activated before writing, the bit line equalizer 102 is activated in response thereto, and the bit lines BL and BLB are precharged at a voltage Vb. At a time t0 after starting to read, the bit line equalization signal BLEQ is deactivated (reset and held, for example, at a low level), and the bit lines BL and BLB are held in a floating state in response thereto.
After that, at a time t1, a word line WL is selected by the row decoder and activated. Here, the selected word line WL is applied with a higher voltage than the power source voltage VDD. Thus, transistors of memory cells connected to the selected word lines WL are activated and switched to be in a conductive state. At the same time, due to a distribution of charges stored in storage nodes STN of the respective memory cells, that is, connection nodes of transistors and capacitors and charges of the bit lines BL and BLB at a precharge level, a potential difference ΔBL arises between the bit lines BL and BLB.
As shown in FIG. 6D, at a time t2 when the potential difference ΔBL of the bit lines BL and BLB reaches a predetermined level, the sense amplifier 150a is supplied with drive voltages SDP and SDN. In response to this, the sense amplifier 150a operates to amplify the potential difference between the bit lines BL and BLB. Therefore, in memory cells other than the selected memory cell, stored data are re-written in accordance with a voltage of the amplified bit line BL or BLB. Namely, the stored data are refreshed.
At a time t3 when read data are amplified by the sense amplifier 150a, a column selection signal YSEL corresponding to a column selected by the column decoder is activated. As a result, in the column selector 160a, transistors Q4 and Q5 corresponding to the selected column become open and a write signal input to the data lines LIO and LIOB in accordance with write data is applied to the bit lines BL and BLB, respectively.
Note that, in FIG. 6C, voltage changes of the bit lines BL and BLB in the case where the write data and read data are different. As shown in FIG. 6E, when the column selection signal YSEL is activated at the time t3, voltages of the bit lines BL and BLB are reversed in accordance with the write signal applied to the data lines LIO and LIOB. Then, the reversed voltages of the bit lines BL and BLB are held by the sense amplifier 150a. Thus, in accordance with the voltage of the bit line BL or BLB, stored charges of a capacitor of the selected memory cell are controlled and the write data are written in the selected memory cell.
After finish writing, at a time t4 as shown in FIG. 6A to FIG. 6F, the selected word line WL is held at a low level by the row decoder, and the drive signals SDP and SDN applied to the sense amplifier 150a are held at a predetermined intermediate potential. Then, in preparation for the next reading or writing, the bit line equalization signal BLEQ is activated and the bit lines BL and BLB are precharged at the voltage Vb in accordance therewith. Consequently, the writing operation is completed.
In the DRAM as a semiconductor memory device disclosed in a Japanese Unexamined Patent Publication No. 3-273594, writing starts after finishing the equalization of bit lines and amplifying read data by the sense amplifier as explained above. Since a predetermined length of writing time has to be secured for sufficiently securing a write charge amount to a selected memory cell, it is hard to realize high speed writing.
In recent years, in a memory for a cache memory and a network, when replacing a SRAM of a high bit unit-cost with a DRAM of a low bit unit-cost with a low power consumption, the DRAM is required to have a high speed random access characteristic. A memory cell of an SRAM is almost the same as a sense amplifier of a DRAM and comprises, for example, six MOS transistors. Random accessing of the SRAM is equivalent to page mode accessing of the DRAM. However, random accessing of the DRAM requires an excessive period for amplifying data read by the sense amplifier after finishing bit line equalization for a normal page mode accessing and a precharge period for the next access by restoring the amplified data as explained above.
Furthermore, it is significant in writing that how much charge stored by writing in a storage node of a memory cell reside until the next reading; and when the residual charge amount becomes a little, stored data cannot be correctly read in the next reading. A charge amount stored in the storage node of the memory cell by writing is determined by the time length from latching of a sense amplifier until resetting of a word line.
However, in a random access mode, as writing becomes high speed, a phenomenon appears that an amount of charge injected into a memory cell decreases and a potential of the storage node after writing becomes insufficient. As a result, a writing operation of a memory cell array at a high speed is hindered. Namely, a sufficient writing period has to be secured for securing a potential of the storage node, and it becomes difficult to shorten the writing period. The disadvantage can be solved to a certain extent by reducing the on-resistance of a transistor of the memory cell, but when considering gate breakdown voltage of the transistor and leakage of stored charges of the storage node of the memory cell, the effects of improvement cannot be expected to be much.